DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 144

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.5.2
Enabling and disabling of IRQ interrupts, WKP interrupts and on-chip peripheral module
interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit
is cleared to 0, and disabled when set to 1.
Figure 5.9 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
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interrupt request is sent to the interrupt controller.
pending. If the I bit is cleared, an interrupt request is accepted.
the priority system is accepted, and other interrupt requests are held pending.
execution of the current instruction has been completed.
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Mode 0