DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 443

IC H8S/2268 MCU FLASH 100QFP

DF2268FA13V

Manufacturer Part Number
DF2268FA13V
Description
IC H8S/2268 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheets

Specifications of DF2268FA13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2268FA13V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 14.2 Transfer Format
14.3.4
ICMR sets the transfer format and transfer rate. It can only be accessed when the ICE bit in ICCR
is 1.
SAR
FS
0
0
1
1
Bit
7
6
I
Bit Name
MLS
WAIT
2
C Bus Mode Register (ICMR)
Section 14 I
SARX
FSX
0
1
0
1
Initial
Value
0
0
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
R/W
R/W
R/W
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Wait Insertion Bit
This bit is valid only in master mode with the I
format.
When WAIT is set to 1, after the fall of the clock for the
final data bit, the IRIC flag is set to 1 in ICCR, and a wait
state begins (with SCL at the low level). When the IRIC
flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred.
If WAIT is cleared to 0, data and acknowledge bits are
transferred consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the
acknowledge bit transfer, regardless of the WAIT setting.
I
SAR and SARX are used as the slave addresses with
the I
Only SAR is used as the slave address with the I
format.
Only SARX is used as the slave address with the I
bus format.
Clock synchronous serial format (SAR and SARX are
invalid)
2
C Transfer Format
2
C bus format.
Rev. 5.00 Sep. 01, 2009 Page 391 of 656
2
C bus format is used.
REJ09B0071-0500
2
C bus
2
C bus
2
C

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