DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 159

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2
1. Set the break address in BARA.
2. Set the break conditions in BCRA.
3. After execution of the instruction that performs a data access on the set address, a PC break
4. After priority determination by the interrupt controller, PC break interrupt exception handling
6.3.3
• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
• When a PC break interrupt is generated at a DTC transfer address
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
• When the SLEEP instruction causes a transition from high speed mode to subactive mode
• When the SLEEP instruction causes a transition from subactive mode to high speed (medium
• When the SLEEP instruction causes a transition to software standby mode or watch mode:
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 3 to 5
(BAMA2 to 0). Set bits 1 and 2 (CSELA1 to 0) to 01, 10, or 11 to specify data access as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
is started.
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
sleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode, and PC break
interrupt handling is executed. After execution of PC break interrupt handling, the instruction
at the address after the SLEEP instruction is executed (figure 6.2 (A)).
(figure 6.2 (B)).
speed) mode (figure 6.2 (C)).
PC Break Interrupt Due to Data Access
Notes on PC Break Interrupt Handling
Operation in Transitions to Power-Down Modes
Rev. 5.00 Sep. 01, 2009 Page 107 of 656
Section 6 PC Break Controller (PBC)
REJ09B0071-0500