DF2268FA13V Renesas Electronics America, DF2268FA13V Datasheet - Page 152

• Manufacturer Part Number: DF2268FA13V
• Description: IC H8S/2268 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2268FA13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
Table 5.9
Legend:
#: Corresponding interrupt is used. Interrupt source is cleared.
O: Corresponding interrupt is used. Interrupt source is not cleared.
X: Corresponding interrupt cannot be used.
*: Don’t care
Usage note: Interrupt sources of the SCI and A/D converter are cleared when the DTC reads or
writes prescribed register, and they do not depend on the DTCE or DISEL bit.
5.6
5.6.1
When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes
effective after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.13 shows an example in which the CMIEA bit in the TCR register of the 8-bit timer is
cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev. 5.00 Sep. 01, 2009 Page 100 of 656
REJ09B0071-0500
Settings
DTC
DTCE
0
1
(The CPU should clear the source flag in the interrupt processing routine.)
Usage Notes
Contention between Interrupt Generation and Disabling
Interrupt Source Selection and Clear Control
DESEL
*
0
1
Interrupt Source Selection
and Clear Control
DTC
X
#
O
CPU
#
X
#