DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 142
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
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Quantity:
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Section 3 MCU Operating Modes
• H8S/2377, H8S/2377R, H8S/2375, H8S/2375R, H8S/2373, and H8S/2373R
Bit
7, 6
5, 4
3
2
1
0
Rev.7.00 Mar. 18, 2009 page 74 of 1136
REJ09B0109-0700
Bit Name
⎯
⎯
FLSHE
⎯
EXPE
RAME
Initial Value
All 1
All 0
0
0
⎯
1
R/W
R/W
R/W
R/W
⎯
R/W
R/W
Descriptions
Reserved
The initial value should not be modified.
Reserved
The initial value should not be modified.
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read from and written to. If this bit is cleared to
0, the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are maintained. This bit should be written to
0 in other than flash memory version.
0: Flash memory control registers are not selected for
1: Flash memory control registers are selected for
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4, this bit is fixed at 1 and cannot
be modified. In modes 3 and 7, this bit can be read
from and written to.
Writing of 0 to this bit when its value is 1 should only
be carried out when an external bus cycle is not being
executed.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
area H'FFFFC8 to H'FFFFCB
area H'FFFFC8 to H'FFFFCB
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