DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 365

IC H8S MCU FLASH 3V 384K 144LQFP

DF2377RVFQ33W

Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2377RVFQ33W

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
13, 12 —
11
10
Bit Name
DTA1
Initial Value
All 0
0
0
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to. However,
the write value should always be 0.
Data Transfer Acknowledge 1
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACR of channel 1.
It the DTA1 bit is set to 1 when DTE1 = 1, the
internal interrupt source is cleared automatically by
DMA transfer. When DTE1 = 1 and DTA1 = 1, the
internal interrupt source does not issue an interrupt
request to the CPU or DTC.
It the DTA1 bit is cleared to 0 when DTE1 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE1 = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA1 bit setting.
The state of the DTME1 bit does not affect the
above operations.
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Rev.7.00 Mar. 18, 2009 page 297 of 1136
Section 7 DMA Controller (DMAC)
REJ09B0109-0700

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