DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 719
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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12.4.8
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 12.11 shows the timing of this output.
12.5
12.5.1
PPG operation can be disabled or enabled using the module stop control register. The initial value
is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 24, Power-Down Modes.
12.5.2
Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
φ
TIOC pin
Input capture
signal
NDR
PODR
PO
Pulse Output Triggered by Input Capture
Usage Notes
Module Stop Mode Setting
Operation of Pulse Output Pins
Figure 12.11 Pulse Output Triggered by Input Capture (Example)
M
M
Section 12 Programmable Pulse Generator (PPG)
N
Rev.7.00 Mar. 18, 2009 page 651 of 1136
N
N
REJ09B0109-0700
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