DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 236
![IC H8S MCU FLASH 3V 384K 144LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller (BSC)
Bit
11
10
9
8
7
6
Rev.7.00 Mar. 18, 2009 page 168 of 1136
REJ09B0109-0700
Bit Name
—
RTCK2
RTCK1
RTCK0
RFSHE
CBRM
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Refresh Counter Clock Select
These bits select the clock to be used to increment
the refresh counter. When the input clock is
selected with bits RTCK2 to RTCK0, the refresh
counter begins counting up.
000: Count operation halted
001: Count on φ/2
010: Count on φ/8
011: Count on φ/32
100: Count on φ/128
101: Count on φ/512
110: Count on φ/2048
111: Count on φ/4096
Refresh Control
Refresh control can be performed. When refresh
control is not performed, the refresh timer can be
used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
CBR Refresh Mode
Selects CBR refreshing performed in parallel with
other external accesses, or execution of CBR
refreshing alone.
When the continuous synchronous DRAM space is
set, this bit can be read/written, but the setting
contents do not affect operations.
0: External access during CAS-before-RAS
1: External access during CAS-before-RAS
refreshing is enabled
refreshing is disabled
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