DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 320

• Manufacturer Part Number: DF2377RVFQ33W
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33W

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.68. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Rev.7.00 Mar. 18, 2009 page 252 of 1136
REJ09B0109-0700
Address bus
CS (area A)
CS (area B)
Figure 6.68 Relationship between Chip Select (CS) and Read (RD)
RD
Overlap period between CS (area B)
and RD may occur
φ
(a) No idle cycle insertion
T
(ICIS1 = 0)
1
Bus cycle A
T
2
T
3
Bus cycle B
T
1
T
2
Address bus
CS (area A)
CS (area B)
RD
φ
T
(b) Idle cycle insertion
1
Bus cycle A
(ICIS1 = 1, initial value)
T
2
T
3
Idle cycle
T
i
Bus cycle B
T
1
T
2