DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 265
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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If a row address hold time or read access time is necessary, making a setting in bits RCD1 and
RCD0 in DRACCR allows from one to three T
maintained, to be inserted between the T
cycle, in which the column address is output. Use the setting that gives the optimum row address
signal hold time relative to the falling edge of the RAS signal according to the DRAM connected
and the operating frequency of this LSI. Figure 6.24 shows an example of the timing when one T
state is set.
Read
Write
Note: n = 2 to 5
Figure 6.24 Example of Timing with One Row Address Output Maintenance State
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
T
p
(RAST = 0, CAST = 0)
Row address
r
cycle, in which the RAS signal goes low, and the T
T
r
rw
states, in which row address output is
Rev.7.00 Mar. 18, 2009 page 197 of 1136
T
rw
Section 6 Bus Controller (BSC)
High
High
T
Column address
c1
REJ09B0109-0700
T
c2
c1
rw
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