DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 290

IC H8S MCU FLASH 3V 384K 144LQFP

DF2377RVFQ33W

Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2377RVFQ33W

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2377RVFQ33W
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.7.7
CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency
count, as shown in table 6.10, by the setting of synchronous DRAM. Depending on the setting, the
CAS latency control cycle (T
AST2 bit of ASTCR. Figure 6.45 shows the CAS latency control timing when synchronous
DRAM of CAS latency 3 is connected.
The initial value of W22 to W20 is H'7. Set the register according to the CAS latency of
synchronous DRAM to be connected.
Table 6.10 Setting CAS Latency
W22
0
1
Rev.7.00 Mar. 18, 2009 page 222 of 1136
REJ09B0109-0700
CAS Latency Control
W21
0
1
0
1
W20
0
1
0
1
0
1
0
1
c1
Description
Connect synchronous DRAM of CAS
latency 1
Connect synchronous DRAM of CAS
latency 2
Connect synchronous DRAM of CAS
latency 3
Connect synchronous DRAM of CAS
latency 4
Reserved (must not used)
Reserved (must not used)
Reserved (must not used)
Reserved (must not used)
) is inserted. WTCRB can be set regardless of the setting of the
CAS Latency Control
Cycle Inserted
0 state
1 state
2 states
3 states

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