DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 341

• Manufacturer Part Number: DF2377RVFQ33W
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33W

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 6.85 Bus Release State Transition Timing when Synchronous DRAM Interface
DQMU, DQML
Precharge-sel
Address bus
SDRAMφ
[1] Low level of BREQ signal is sampled at rise of φ.
[2] PALL command is issued.
[3] Bus control signal returns to be high at end of external space access cycle.
[4] BACK signal is driven low, releasing bus to external bus master..
[5] BREQ signal state is also sampled in external bus released state.
[6] High level of BREQ signal is sampled.
[7] BACK signal is driven high, ending external bus release cycle.
[8] When there is external access or refresh request of internal bus master during
[9] BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
Note: In the H8S/2373 Group, the synchronous DRAM interface is not supported.
Data bus
BREQO
BREQ
BACK
external bus release while the BREQOE bit is set to 1, BREQO signal goes low.
signal is asserted because of auto-refreshing request, it retains low until auto-refresh cycle starts up.
At least one state from sampling of BREQ signal.
RAS
CAS
CKE
φ
WE
External space read
NOP
T
1
[1]
T
2
[2]
PALL
[3]
address
NOP
Row
[4]
External bus released state
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
High impedance
[5]
Rev.7.00 Mar. 18, 2009 page 273 of 1136
[8]
Section 6 Bus Controller (BSC)
[6]
[7]
NOP
REJ09B0109-0700
[9]
CPU
cycle