DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 431

IC H8S MCU FLASH 3V 384K 144LQFP

DF2377RVFQ33W

Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2377RVFQ33W

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

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Part Number:
DF2377RVFQ33W
Manufacturer:
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Quantity:
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Part Number:
DF2377RVFQ33WV
Manufacturer:
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Quantity:
10 000
EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDDAR for a channel on which EXDMA transfer is in progress. The initial values of EDDAR
are undefined.
8.3.3
EDTCR specifies the number of transfers. The function differs according to the transfer mode. Do
not write to EDTCR for a channel on which EXDMA transfer is in progress.
Normal Transfer Mode:
Bit
31
to
24
23
to
0
Bit Name
EXDMA Transfer Count Register (EDTCR)
Initial Value
All 0
All 0
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
24-Bit Transfer Counter
These bits specify the number of transfers. Setting
H'000001 specifies one transfer. Setting H'000000
means no specification for the number of transfers,
and the transfer counter function is halted. In this
case, there is no transfer end interrupt by the
transfer counter. Setting H'FFFFFF specifies the
maximum number of transfers, that is 16,777,215.
During EXDMA transfer, this counter shows the
remaining number of transfers.
This counter can be read at all times. When
reading EDTCR for a channel on which EXDMA
transfer processing is in progress, a longword-size
read must be executed.
Rev.7.00 Mar. 18, 2009 page 363 of 1136
Section 8 EXDMA Controller (EXDMAC)
REJ09B0109-0700

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