DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 288

IC H8S MCU FLASH 3V 384K 144LQFP

DF2377RVFQ33W

Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of DF2377RVFQ33W

Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
DF2377RVFQ33W
Manufacturer:
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Quantity:
10 000
Part Number:
DF2377RVFQ33WV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
6.7.5
When the DCTL pin is fixed to 1, synchronous clock (SDRAMφ) is output from the CS5 pin.
When the frequency multiplication factor of the PLL circuit of this LSI is set to ×1 or ×2,
SDRAMφ is 90° phase shift from φ. Therefore, a stable margin is ensured for the synchronous
DRAM that operates at the rising edge of clocks. Figure 6.43 shows the relationship between φ
and SDRAMφ. When the frequency multiplication factor of the PLL circuit is ×4, the phase of
SDRAMφ and that of φ are the same.
When the CLK pin of the synchronous DRAM is directly connected to SDRAMφ of this LSI, it is
recommended to set the frequency multiplication factor of the PLL circuit to ×1 or ×2.
Note: SDRAMφ output timing is shown when the frequency multiplication factor of the PLL
6.7.6
The four states of the basic timing consist of one T
output cycle) state, and the T
When areas 2 to 5 are set for the continuous synchronous DRAM space, settings of the WAITE bit
of BCR, RAST, CAST, RCDM bits of DRAMCR, and the CBRM bit of REFCR are ignored.
Figure 6.44 shows the basic timing for synchronous DRAM.
Rev.7.00 Mar. 18, 2009 page 220 of 1136
REJ09B0109-0700
Figure 6.43 Relationship between φ and SDRAMφ (when PLL Frequency Multiplication
circuit is ×1 or ×2.
Synchronous DRAM Clock
Basic Timing
SDRAMφ
φ
c1
and two T
Factor Is ×1 or ×2)
c2
(column address output cycle) states.
T cyc
p
(precharge cycle) state, one T
1/4 T cyc (90°)
r
(row address

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