DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 16

• Manufacturer Part Number: DF2377RVFQ33W
• Description: IC H8S MCU FLASH 3V 384K 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2377RVFQ33W

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
16.3.5 I2C Bus Status
Register (ICSR)
16.4.7 Example of
Use
Figure 16.14 Sample
Flowchart for Master
Transmit Mode
Rev.7.00 Mar. 18, 2009 page xiv of lxvi
REJ09B0109-0700
Page
782
783
797
Revision (See Manual for Details)
Table amended
Bit
7
Table amended
Figure amended
Note: * Ensure that no interrupts occur between when BBSY
Bit
2
No
Bit Name
TDRE
Bit Name
AL
Read BBSY in ICCRB
Set MST = 1 and TRS
Write BBSY = 1
= 1 in ICCRA.
and SCP = 0.
BBSY=0 ?
Initialize
Start
is cleared to 0 and start condition [3].
Yes
Initial Value
0
Initial Value
0
[1]
[2]
[3]
R/W
R/W
R/W
R/W
[1]
[2]
[3]
[4]
Description
Transmit Data Register Empty
[Setting condition]
•
•
•
[Clearing conditions]
•
•
Description
Arbitration Lost Flag
This flag indicates that arbitration was lost in master
mode.
When two or more master devices attempt to seize
the bus at nearly the same time, if the I
interface detects data differing from the data it sent, it
sets AL to 1 to indicate that the bus has been taken
by another master.
[Setting conditions]
•
•
[Clearing condition]
•
Test the status of the SCL and SDA lines.*
Select master transmit mode.*
Start condition issuance.*
Select transmit data for the first byte (slave address + R/W),
and clear TDRE to 0.
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
When TRS has been set
When a transition from the receive mode to the
transmit mode has been made in the slave mode
When 0 is written in TDRE after reading TDRE = 1
When data is written in ICDRT
If the internal SDA and SDA pin disagree at the
rise of SCL in master transmit mode
When the internal SDA high in master mode while
a start condition is detected
When 0 is written in AL/OVE after reading
AL/OVE=1
2
C bus