DF2377RVFQ33W Renesas Electronics America, DF2377RVFQ33W Datasheet - Page 284
DF2377RVFQ33W
Manufacturer Part Number
DF2377RVFQ33W
Description
IC H8S MCU FLASH 3V 384K 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2377RVFQ33W
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.7
In the H8S/2378R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
6.7.1
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.7. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.7
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The (OE) pin of the synchronous DRAM is used as the CKE signal, and the CS5 pin is
used as synchronous DRAM clock (SDRAMφ). The bus specifications for continuous
synchronous DRAM space conform to the settings for area 2. The pin wait and program wait for
the continuous synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.
Rev.7.00 Mar. 18, 2009 page 216 of 1136
REJ09B0109-0700
RMTS2
0
1
Synchronous DRAM Interface
Setting Continuous Synchronous DRAM Space
RMTS1
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
0
1
0
1
RMTS0
1
0
1
0
1
0
1
Normal space Normal space Normal space
Normal space Normal space
DRAM space
Area 5
Continuous synchronous DRAM space
Mode settings of synchronous DRAM
DRAM space
Reserved (setting prohibited)
Continuous DRAM space
Area 4
DRAM space
DRAM space
Area 3
DRAM space
DRAM space
DRAM space
Area 2
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