MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 100
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Cache
output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access
in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded
into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary
storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated
line fill buffer are examined. Thus, each fetch address examines the tag memory array and the associated
line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit in the
memory array or the associated line-fill buffer is serviced in a single cycle. Because the line fill buffer
maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without waiting
for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the cache
initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst
reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released
after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests
while the remainder of the line is being fetched and loaded into the fill buffer.
4.2
Three supervisor registers define the operation of the cache and local bus controller: the cache control
register (CACR) and two access control registers (ACR0, ACR1).
4-2
31
Memory Map/Register Definition
Local Address Bus
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
10
43
2
Figure 4-1. 2-Kbyte Cache Block Diagram
1
0
Fill Hit
=
I or D Line
31
31
Tag Hit
TAG
=
Buffer
Address
11
4
0
127
Table 4-1
I or D Line Buffer Storage
External Data[31:0]
below shows the memory map
31
Local Data Bus
DATA
MUX
MUX
Freescale Semiconductor
0
0
511
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