MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 385

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

20.5.19 GPT Port Data Direction Register (GPTDDR)
20.6
The General Purpose Timer (GPT) module is a 16-bit, 4-channel timer with input capture and output
compare functions and a pulse accumulator.
20.6.1
The prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. The GPTSCR2[PR] bits select the
prescaler divisor.
20.6.2
Clearing an I/O select bit, IOSn, configures channel n as an input capture channel. The input capture
function captures the time at which an external event occurs. When an active edge occurs on the pin of an
input capture channel, the timer transfers the value in the GPT counter into the GPT channel registers,
GPTCn.
The minimum pulse width for the input capture input is greater than two module clocks.
The input capture function does not force data direction. The GPT port data direction register controls the
data direction of an input capture pin. Pin conditions such as rising or falling edges can trigger an input
capture only on a pin configured as an input.
An input capture on channel n sets the CnF flag. The CnI bit enables the CnF flag to generate interrupt
requests.
Freescale Semiconductor
Pulse Accumulator Function
Bit(s)
7–4
3–0
Functional Description
Prescaler
Input Capture
GPT Function
Name
DDRT
—
Address
Reset
Figure 20-21. GPT Port Data Direction Register (GPTDDR)
Field
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
R/W
Reserved, should be cleared.
Control the port logic of PORTTn. Reset clears the PORTTn data direction register,
configuring all GPT port pins as inputs. These bits are read anytime, write anytime.
1 Corresponding pin configured as output
0 Corresponding pin configured as input
Table 20-22. GPTDDR Field Descriptions
7
6
—
—
—
IPSBAR + 0x1A_001E, 0x1B_001E
5
0000_0000
Description
4
R/W
General Purpose Timer Modules (GPTA and GPTB)
PAI
3
IC/OC
DDRT
—
0
20-17