MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 632

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Debug Support
Table 30-12
Figure 30-9
Table 30-13
30.4.7
The TDR, shown in
corresponds with the ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug
module. The TDR controls the actions taken under the defined conditions. Breakpoint logic may be
configured as a one- or two-level trigger. TDR[31–16] define the second-level trigger and bits 15–0 define
the first-level trigger.
30-14
DRc[4–0]
31–0
31–0 Address PC breakpoint address. The 32-bit address to be compared with the PC as a breakpoint trigger.
Bits
Bits
DRc[4–0]
Reset
Field
R/W Write. PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through
Reset
Field
R/W
Name
Mask
Trigger Definition Register (TDR)
Name
shows PBMR.
the BDM port using the
Set
describes PBR fields.
describes PBMR fields.
31
31
Descriptions.”
Write. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG
PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the
appropriate PC bit. Set PBMR bits cause PBR bits to be ignored.
Figure 30-10. Program Counter Breakpoint Mask Register (PBMR)
Table
Figure 30-9. Program Counter Breakpoint Register (PBR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
30-11, configures the operation of the hardware breakpoint logic that
instruction and via the BDM port using the wdmreg command.
RDMREG
Table 30-13. PBMR Field Descriptions
Table 30-12. PBR Field Descriptions
and
WDMREG
commands using values shown in
Program Counter
0x08 (PBR)
Description
Description
Mask
0x09
—
—
Section 30.5.3.3, “Command
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