MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 373

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

20.5.1
Freescale Semiconductor
1
2
S = CPU supervisor mode access only.
Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
Bit(s)
0x1A_001C
0x1A_001D
7–4
3–0
0x1A_001A
0x1A_001B
0x1A_001E
0x1A_001F
0x1A_0017
0x1A_0018
0x1A_0019
GPTA
GPT Input Capture/Output Compare Select Register (GPTIOS)
IPSBAR Offset
Address
Reset
Figure 20-2. GPT Input Capture/Output Compare Select Register (GPTIOS)
Field
R/W
Name
IOS
—
0x1B_001C
0x1B_001D
0x1B_001A
0x1B_001B
0x1B_001E
0x1B_001F
0x1B_0017
0x1B_0018
0x1B_0019
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
GPTB
7
Table 20-3. GPT Modules Memory Map (continued)
Reserved, should be cleared.
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the
corresponding timer channels. These bits are read anytime (always read 0x00), write
anytime.
1 Output compare enabled
0 Input capture enabled
Table 20-4. GPTIOS Field Descriptions
—
Pulse Accumulator Counter Register High (GPTPACNTH)
Pulse Accumulator Counter Register Low (GPTPACNTL)
IPSBAR + 0x401A_0000, 0x401B_0000
Pulse Accumulator Control Register (GPTPACTL)
Pulse Accumulator Flag Register (GPTPAFLG)
GPT Port Data Direction Register (GPTDDR)
GPT Channel 3 Register Low (GPTC3L)
GPT Port Data Register (GPTPORT)
GPT Test Register (GPTTST)
0000_0000
4
R/W
Reserved
Bits 7–0
3
Description
General Purpose Timer Modules (GPTA and GPTB)
(2)
IOS
0
Access
—
S
S
S
S
S
S
S
S
1
20-5