MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 72
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
This section includes the assumptions concerning the timing values and the execution time details.
2.3.5.1
For the timing data presented in this section, these assumptions apply:
2.3.5.2
Table 2-12
2-26
•
1. The OEP is loaded with the opword and all required extension words at the beginning of each
2. The OEP does not experience any sequence-related pipeline stalls. The most common example of
3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.
4. All operand data accesses are aligned on the same byte boundary as the operand size; for example,
R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation
performing a read-modify-write function is denoted as (1/1).
instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or
extension words.
stall involves consecutive store operations, excluding the MOVEM instruction. For all STORE
operations (except MOVEM), certain hardware resources within the processor are marked as busy
for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store
instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it is
stalled until the resource again becomes available. Thus, the maximum pipeline stall involving
consecutive STORE operations is two cycles. The MOVEM instruction uses a different set of
resources and this stall does not apply.
Thus, the timing details provided in this section assume that an infinite zero-wait state memory is
attached to the processor core.
16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4
addresses.
The processor core decomposes misaligned operand references into a series of aligned accesses as
shown in
lists execution times for MOVE.{B,W} instructions;
Timing Assumptions
MOVE Instruction Execution Times
For all tables in this section, the execution time of any instruction using the
PC-relative effective addressing modes is the same for the comparable
An-relative mode.
Table
2-11.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
address[1:0]
01 or 11
01 or 11
Table 2-11. Misaligned Operand References
10
Word
Long
Long
Size
NOTE
Operations
Word, Word
Byte, Word,
Byte, Byte
Byte
Bus
Table 2-13
1(0/1) if write
2(0/2) if write
1(0/1) if write
2(1/0) if read
3(2/0) if read
2(1/0) if read
Additional
C(R/W)
lists timings for MOVE.L.
Freescale Semiconductor
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