MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 417
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 417 of 766
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The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following
expression:
22.4.3
The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time
between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer
and the beginning of the next, are both independently programmable.
The chip select to clock delay enable bit in the command RAM, QCR[DSCK], enables the programmable
delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the
period of delay before the leading edge of QSPI_CLK. The following expression determines the actual
delay before the QSPI_CLK leading edge:
QDLYR[QCD] has a range of 1–127.
When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period
is used.
The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period
from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can
be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive
transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the
user can choose to delay a standard period after serial transfer is complete or can specify a delay period.
Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard
delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to
calculate the delay when DT equals 1:
Freescale Semiconductor
Table 22-10. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate
Transfer Delays
Delay after transfer
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QMR[BAUD]
QSPI_CS-to-QSPI_CLK delay
QMR [BAUD]
255
16
32
2
4
8
=
Internal Bus Clock = 80 MHz
-----------------------------------------------------------------------------------
2
=
×
32
----------------------------------------------- -
[desired QSPI_CLK baud rate]
×
QDLYR[DTL]
f
sys
=
f
sys
QDLYR[QCD]
------------------------------------ -
QSPI_CLK
f
156.9 kHz
sys
2.5 MHz
20 MHz
10 MHz
1.25 Hz
5 MHz
(DT = 1)
Queued Serial Peripheral Interface (QSPI)
Eqn. 22-1
Eqn. 22-2
Eqn. 22-3
22-13
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