MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 641
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any
revision level perform a
30.5.3.3.1
Read the selected address or data register and return the 32-bit result. A bus error response is returned if
the CPU core is not halted.
Command/Result Formats:
Command Sequence:
Operand Data:
Result Data:
30.5.3.3.2
The operand longword data is written to the specified address or data register. A write alters all 32 register
bits. A bus error response is returned if the CPU core is not halted.
Command Format:
Freescale Semiconductor
Command
15
Result
Read A/D Register (
Write A/D Register (
0x2
The BDM status bit (S) is 0 for normally completed commands; S = 1 for
illegal commands, not-ready responses, and transfers with bus-errors.
Section 30.5.2, “BDM Serial
format.
15
12
None
The contents of the selected register are returned as a longword value,
most-significant word first.
0x2
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOP
Figure 30-18. RAREG
Figure 30-19. WAREG
Figure 30-17. RAREG
and return an illegal command response.
RAREG/RDREG
11
12
???
RAREG
WAREG
11
0x0
/
/
RDREG
WDREG
0x1
Interface,” describes the receive packet
MS RESULT
/
8
D[31:16]
NOTE
RDREG Command Sequence
D[15:0]
/
/
RDREG Command Format
WDREG Command Format
BERR
XXX
XXX
)
)
D[31:16]
8
D[15:0]
7
7
0x8
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
0x8
4
4
A/D
3
A/D
3
2
2
Register
Register
Debug Support
0
0
30-23
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