MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 651
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Command Sequence:
Operand Data:
Result Data:
BDM Accesses of the Stack Pointer Registers (A7: SSP, USP)
The processor’s Version 2 ColdFire core supports two unique stack pointer (A7) registers: the supervisor
stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two
programmable-visible 32-bit registers does not uniquely identify one as the SSP and the other as the USP.
Rather, the hardware uses one 32-bit register as the currently-active A7 and the other register is named
simply the “other_A7”. Thus, the contents of the two hardware registers is a function of the operating mode
of the processor:
if SR[S] = 1
The BDM programming model supports reads and writes to the A7 and other_A7 registers directly. It is
the responsibility of the external development system to determine the mapping of the two hardware
registers (A7, other_A7) to the two program-visible definitions (supervisor and user stack pointers), based
on the Supervisor bit of the status register.
BDM Accesses of the EMAC Registers
The presence of rounding logic in the output datapath of the EMAC requires that special care be taken
during any BDM-initiated reads and writes of its programming model. In particular, it is necessary that any
result rounding modes be disabled during the read/write process so the exact bit-wise contents of the
EMAC registers are accessed.
As an example, any BDM read of an accumulator register (ACCn) must be preceded by two commands
accessing the MAC status register. Specifically, the following BDM sequence is required:
BdmReadACCn (
Freescale Semiconductor
then
else
rcreg
wcreg
RCREG
???
macsr;
#0,macsr;
A7 = Supervisor Stack Pointer
other_A7 = User Stack Pointer
A7 = User Stack Pointer
other_A7 = Supervisor Stack Pointer
’NOT READY’
The only operand is the 32-bit Rc control register select field.
Control register contents are returned as a longword, most-significant word first.
The implemented portion of registers smaller than 32 bits is guaranteed correct;
other bits are undefined.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
MS ADDR
Figure 30-34.
// read macsr contents & save
// disable all rounding modes
’NOT READY’
MS ADDR
RCREG
Command Sequence
REGISTER
CONTROL
READ
’NOT READY’
MS RESULT
NEXT CMD
BERR
XXX
XXX
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
Debug Support
30-33
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