MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 247
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Table 14-2
Freescale Semiconductor
Development serial
input/Test data
Development serial
output/Test data
Test clock
Debug data
Processor status
outputs
Test
QADC analog reference VRH, VRL
QADC analog supply
PLL analog supply
QADC positive supply
Flash erase/program
power
Flash array power
and ground
Standby power
Positive supply
Ground
lists signals in alphabetical order by abbreviated name.
Signal Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 14-1. MCF5282 Signal Description (continued)
DSI/TDI
DSO/TDO
TCLK
DDATA[3:0]
PST[3:0]
TEST
VDDA, VSSA
VDDPLL, VSSPLL Isolate the PLL analog circuitry from
VDDH
VPP
VDDF, VSSF
VSTBY
VDD
VSS
Abbreviation
Power and Reference Signals
Provides single-bit communication for
debug module commands (DSI).
Provides serial data port for loading
JTAG boundary scan, bypass, and
instruction registers (TDI).
Provides single-bit communication for
debug module responses (DSO).
Provides serial data port for outputting
JTAG logic data (TDO).
JTAG test logic clock.
addresses, data, and breakpoint
status.
Indicate core status.
Reserved, should be connected to
VSS.
High (VRH) and low (VRL) reference
potentials for the analog converter.
digital power supply noise.
digital power supply noise.
Supplies positive power to the ESD
structures in the QADC pads.
Used for Flash stress testing.
Supply power and ground to Flash
array.
Provides standby voltage to RAM array
if VDD is lost.
Supplies positive power to the core
logic and I/O pads.
Negative supply.
Display captured processor
Test Signals
Isolate the QADC analog circuitry from
Function
Ground
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
Signal Descriptions
14-30
14-30
14-30
14-31
14-31
14-31
14-32
14-32
14-32
14-32
14-32
14-32
14-32
14-32
14-32
Page
14-7
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