MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 319
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 319 of 766
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17.4.2
When an event occurs that sets a bit in EIR, an interrupt occurs if the corresponding bit in the interrupt
mask register (EIMR) is also set. Writing a 1 to an EIR bit clears it; writing 0 has no effect. This register
is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and
internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB,
and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,
BABR, BABT, LC, and RL. Interrupts resulting from internal errors are HBERR and UN.
Some of the error interrupts are independently counted in the MIB block counters:
Software may choose to mask off these interrupts because these errors are visible to network management
via the MIB counters.
Freescale Semiconductor
IPSBAR
Offset:
Reset
Reset
•
•
•
•
•
•
W w1c
W
R
R
HBERR - IEEE_T_SQE
BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)
BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)
LATE_COL - IEEE_T_LCOL
COL_RETRY_LIM - IEEE_T_EXCOL
XFIFO_UN - IEEE_T_MACERR
0x1004
IPSBAR Offset
ERR
HB
31
15
0
0
0
0x12DC
Ethernet Interrupt Event Register (EIR)
0x12E0
BABR BABT GRA
w1c
30
14
0
0
0
w1c
29
13
0
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Flow control pause frames received (IEEE_R_FDXFC)
Octet count for frames received without error (IEEE_R_OCTETS_OK)
Figure 17-2. Ethernet Interrupt Event Register (EIR)
Table 17-4. MIB Counters Memory Map (continued)
w1c
28
12
0
0
0
TXF
w1c
27
11
0
0
0
TXB
w1c
26
10
0
0
0
RXF
w1c
25
0
0
0
9
RXB
w1c
24
0
0
0
8
Register
w1c
MII
23
0
0
0
7
ERR
w1c
EB
22
0
0
0
6
w1c
LC
21
0
0
0
5
w1c
RL
20
0
0
0
4
Fast Ethernet Controller (FEC)
w1c
UN
19
0
0
0
3
Access: User read/write
18
0
0
2
0
0
17
0
0
0
0
1
16
17-9
0
0
0
0
0
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