MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 14
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 14 of 766
- Download datasheet (9Mb)
15.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 SDRAM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
xiv
14.2.13Analog-to-Digital Converter Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.14Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.15Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
14.2.16Power and Reference Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
15.1.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1.2 Block Diagram and Major Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
14.2.12.1 DMA Timer 0 Input (DTIN0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
14.2.12.2 DMA Timer 0 Output (DTOUT0) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
14.2.12.3 DMA Timer 1 Input (DTIN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27
14.2.12.4 DMA Timer 1 Output (DTOUT1) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.12.5 DMA Timer 2 Input (DTIN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.12.6 DMA Timer 2 Output (DTOUT2) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.12.7 DMA Timer 3 Input (DTIN3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.12.8 DMA Timer 3 Output (DTOUT3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.13.1 QADC Analog Input (AN0/ANW) . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.13.2 QADC Analog Input (AN1/ANX) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28
14.2.13.3 QADC Analog Input (AN2/ANY) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.13.4 QADC Analog Input (AN3/ANZ) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.13.5 QADC Analog Input (AN52/MA0) . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.13.6 QADC Analog Input (AN53/MA1) . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.13.7 QADC Analog Input (AN55/TRIG1) . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.13.8 QADC Analog Input (AN56/TRIG2) . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.14.1 JTAG_EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29
14.2.14.2 Development Serial Clock/Test Reset (DSCLK/TRST) . . . . . . . . 14-30
14.2.14.3 Breakpoint/Test Mode Select (BKPT/TMS) . . . . . . . . . . . . . . . . . 14-30
14.2.14.4 Development Serial Input/Test Data (DSI/TDI) . . . . . . . . . . . . . . . 14-30
14.2.14.5 Development Serial Output/Test Data (DSO/TDO) . . . . . . . . . . . 14-30
14.2.14.6 Test Clock (TCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30
14.2.14.7 Debug Data (DDATA[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
14.2.14.8 Processor Status Outputs (PST[3:0]) . . . . . . . . . . . . . . . . . . . . . . 14-31
14.2.15.1 Test (TEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31
14.2.16.1 QADC Analog Reference (VRH, VRL) . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.2 QADC Analog Supply (VDDA, VSSA) . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.3 PLL Analog Supply (VDDPLL, VSSPLL) . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.4 QADC Positive Supply (VDDH) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.5 Power for Flash Erase/Program (VPP) . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.6 Power and Ground for Flash Array (VDDF, VSSF) . . . . . . . . . . . 14-32
14.2.16.7 Standby Power (VSTBY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.8 Positive Supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
14.2.16.9 Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Synchronous DRAM Controller Module
Chapter 15
Freescale Semiconductor
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