MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 9
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.4 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.5 Internal Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.6 System Access Control Unit (SACU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Freescale Semiconductor
7.3.3 Summary of Peripheral State During Low-Power Modes . . . . . . . . . . . . . . . . 7-13
8.4.1 Internal Peripheral System Base Address Register (IPSBAR) . . . . . . . . . . . . . 8-2
8.4.2 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.4.3 Core Reset Status Register (CRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.4.4 Core Watchdog Control Register (CWCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
8.4.5 Core Watchdog Service Register (CWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
8.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
8.5.2 Arbitration Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.5.3 Bus Master Park Register (MPARK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.6.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
8.6.3 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
7.3.2.7 DMA Controller (DMAC0–DMA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.3.2.8 UART Modules (UART0, UART1, and UART2) . . . . . . . . . . . . . . . . . . 7-8
7.3.2.9 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.2.10 Queued Serial Peripheral Interface (QSPI) . . . . . . . . . . . . . . . . . . . . 7-8
7.3.2.11 DMA Timers (DMAT0–DMAT3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3.2.12 Interrupt Controllers (INTC0, INTC1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2.13 Fast Ethernet Controller (FEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2.14 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2.15 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2.16 Chip Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.3.2.17 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.2.18 Edge Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.2.19 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.2.20 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) . . . . . 7-10
7.3.2.21 Queued Analog-to-Digital Converter (QADC) . . . . . . . . . . . . . . . . . . 7-11
7.3.2.22 General Purpose Timers (GPTA and GPTB) . . . . . . . . . . . . . . . . . . 7-11
7.3.2.23 FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.3.2.24 ColdFire Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.2.25 BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.2.26 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
8.5.2.1 Round-Robin Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.5.2.2 Fixed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
8.6.3.1 Master Privilege Register (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
8.6.3.2 Peripheral Access Control Registers (PACR0–PACR8) . . . . . . . . . . . 8-13
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
System Control Module (SCM)
Chapter 8
ix
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