MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 288
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Synchronous DRAM Controller Module
Figure 15-8
request becomes active. The request is delayed by the precharge to
SDRAM bank by the CAS bits. The
DCR[RTIM] is inserted before the next
is initiated, but does not generate an SDRAM access until T
active during the
SDRAM_CS[0] or [1]
15.2.3.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at the same time
to perform an internal refresh operation and to maintain the integrity of the data stored in the SDRAM. The
DRAM controller supports self-refresh with DCR[IS]. When IS is set, the
SDRAM. When IS is cleared, the
self-refresh operation.
15-16
CLKOUT
DRAMW
A[23:0]
SRAS
SCAS
shows the auto-refresh timing. In this case, there is an SDRAM access when the refresh
REF
command, it is passed to both blocks of external SDRAM.
PALL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
t
RCD
= 2
SELFX
Figure 15-8. Auto-Refresh Operation
ACTV
command is sent to the DRAM controller.
REF
REF
command is then generated and the delay required by
command is generated. In this example, the next bus cycle
RC
is finished. Because both chip selects are
t
RC
ACTV
= 6
delay programmed into the active
SELF
command is sent to the
Figure 15-9
Freescale Semiconductor
shows the
ACTV
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