MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 429
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 429 of 766
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23.3.4
The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus
clock as the clocking source for the transmitter and receiver. See
Clock
for both, set UCSRn to 0xDD.
23.3.5
The UCRs supply commands to the UART. Only multiple commands that do not conflict can be specified
in a single write to a UCRn. For example,
specified in one command.
Freescale Semiconductor
RXRDY
FFULL
Field
Field
RCS
TCS
7–4
3–0
1
0
IPSBAR
Offset:
Reset:
Source.” The transmitter and receiver can use different clock sources. To use the internal bus clock
FIFO full.
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.
Receiver ready.
0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receive buffer FIFO.
Receiver clock select. Selects the clock source for the receiver.
1101 Prescaled internal bus clock (f
1110 DTINn divided by 16
1111 DTINn
Transmitter clock select. Selects the clock source for the transmitter.
1101 Prescaled internal bus clock (f
1110 DTINn divided by 16
1111 DTINn
W
R
UART Clock Select Registers (UCSRn)
UART Command Registers (UCRn)
0x00_0204 (UCSR0)
0x00_0244 (UCSR1)
0x00_0284 (UCSR2)
Note: The RCS and TCS reset values are set so the receiver and transmiter use the prescaled internal bus
7
clock as their clock source.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 23-6. UART Clock Select Registers (UCSRn)
6
Table 23-5. USRn Field Descriptions (continued)
See Note
RCS
Table 23-6. UCSRn Field Descriptions
sys
sys
5
)
)
RESET TRANSMITTER
4
Description
Description
3
and
Section 23.4.1, “Transmitter/Receiver
ENABLE TRANSMITTER
2
See Note
TCS
Access: User write-only
1
cannot be
UART Modules
0
23-9
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