MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 65
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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execution until all previous operations, including all pending write operations, are complete. If any
previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.
2.3.4.2
Any attempted execution transferring control to an odd instruction address (if bit 0 of the target address is
set) results in an address error exception.
Any attempted use of a word-sized index register (Xn.w) or a scale factor of eight on an indexed effective
addressing mode generates an address error, as does an attempted execution of a full-format indexed
addressing mode, which is defined by bit 8 of extension word 1 being set.
If an address error occurs on a JSR instruction, the Version 2 ColdFire processor calculates the target
address then the return address is pushed onto the stack. If an address error occurs on an RTS instruction,
the Version 2 ColdFire processor overwrites the faulting return PC with the address error stack frame.
2.3.4.3
The ColdFire variable-length instruction set architecture supports three instruction sizes: 16, 32, or 48 bits.
The first instruction word is known as the operation word (or opword), while the optional words are known
as extension word 1 and extension word 2. The opword is further subdivided into three sections: the upper
four bits segment the entire ISA into 16 instruction lines, the next 6 bits define the operation mode
(opmode), and the low-order 6 bits define the effective address. See
definition is shown in
Freescale Semiconductor
Opword[Line]
15
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
14
Address Error Exception
Illegal Instruction Exception
Line
Move Byte
Move Word
Add (ADDQ) and Subtract Quick (SUBQ), Set according to Condition Codes (Scc)
Move Quick (MOVEQ), Move with sign extension (MVS) and zero fill (MVZ)
Logical OR (OR)
Bit manipulation, Arithmetic and Logical Immediate
Move Long
Miscellaneous
PC-relative change-of-flow instructions
Conditional (Bcc) and unconditional (BRA) branches, subroutine calls (BSR)
Subtract (SUB), Subtract Extended (SUBX)
13
Figure 2-17. ColdFire Instruction Operation Word (Opword) Format
Table
12
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
2-8.
11
Table 2-8. ColdFire Opword Line Definition
10
OpMode
9
8
Instruction Class
7
6
5
Figure
Mode
4
2-17. The opword line
Effective Address
3
2
Register
1
ColdFire Core
0
2-19
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