MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 654

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MCF5282CVF80J

Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5282CVF80J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Debug Support
Command Sequence:
Operand Data:
Result Data:
30.5.3.3.12 Write Debug Module Register (
The operand (longword) data is written to the specified debug module register. All 32 bits of the register
are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU
accesses are performed using the WDEBUG instruction.
Command Format:
Table 30-3
Command Sequence:
Operand Data:
Result Data:
30-36
15
shows the definition of the DRc write encoding.
0x2
WDMREG
???
12
None
The contents of the selected debug register are returned as a longword value. The
data is returned most-significant word first.
Longword data is written into the specified debug register. The data is supplied
most-significant word first.
Command complete status (0xFFFF) is returned when register write is complete.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
11
Figure 30-39.
Figure 30-40.
Figure 30-38.
RDMREG
???
’NOT READY’
’ILLEGAL’
MS DATA
0xC
XXX
WDMREG
WDMREG
RDMREG
MS RESULT
’ILLEGAL’
8
D[31:16]
D[15:0]
WDMREG
XXX
XXX
BDM Command Format
Command Sequence
Command Sequence
’NOT READY’
’NOT READY’
NEXT CMD
7
LS DATA
)
100
’NOT READY’
LS RESULT
NEXT CMD
NEXT CMD
5
’CMD COMPLETE’
NEXT CMD
4
Freescale Semiconductor
DRc
0

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