MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 435
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 435 of 766
- Download datasheet (9Mb)
23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload value. UBG1n
and UBG2n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation,
as described in
23.3.12 UART Input Port Register (UIPn)
The UIPn registers show the current state of the UCTSn input.
Freescale Semiconductor
IPSBAR
IPSBAR
IPSBAR
Offset:
Offset:
Offset:
Reset:
Reset:
Reset:
W
W
W
R
R
R
0x00_0218 (UBG10)
0x00_0258 (UBG11)
0x00_0298 (UBG12)
0x00_021C (UBG20)
0x00_025C (UBG21)
0x00_029C (UBG22)
0x00_0234 (UIP0)
0x00_0274 (UIP1)
0x00_02B4 (UIP2)
The minimum value loaded on the concatenation of UBG1n with UBG2n is
0x0002. The UBG2n reset value of 0x00 is invalid and must be written to
before the UART transmitter or receiver are enabled. UBG1n and UBG2n
are write-only and cannot be read by the CPU.
Section 23.4.1.2.1, “Internal Bus Clock Baud
0
0
1
1
7
7
7
Figure 23-13. UART Baud Rate Generator Registers (UBG1n)
Figure 23-14. UART Baud Rate Generator Registers (UBG2n)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
6
0
6
0
6
1
1
Figure 23-15. UART Input Port Registers (UIPn)
0
0
1
1
5
5
5
NOTE
0
0
1
1
4
4
4
Divider MSB
Divider LSB
Rates.”
0
0
1
1
3
3
3
0
0
1
1
2
2
2
Access: User write-only
Access: User write-only
Access: User read-only
0
0
1
1
1
1
1
UART Modules
CTS
0
0
1
0
0
0
23-15
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