MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 409

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Figure 22-3
22.3.2
The QDLYR is used to initiate master mode transfers and to set various delay parameters.
Freescale Semiconductor
IPSBAR
Field
14–8
QCD
Offset:
SPE
DTL
7–0
QSPI_DOUT
Reset
15
QSPI_CLK
QSPI_DIN
QSPI_CS
W
R
0x00_0344 (QDLYR)
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.
The QSPI clears this bit automatically when a transfer completes. The user can also clear this bit to abort transfer
unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].
QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from
assertion of the chip selects to valid QSPI_CLK transition. See
setting this bit field.
Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the
serial transfer.
SPE
15
0
QSPI Delay Register (QDLYR)
shows an example of a QSPI clocking and data transfer.
14
0
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
msb
15
15
13
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
A
Figure 22-3. QSPI Clocking and Data Transfer Example
14
14
12
13
13
0
Figure 22-4. QSPI Delay Register (QDLYR)
Table 22-4. QDLYR Field Descriptions
QCD
12
12
11
0
11
11
10
1
10
10
9
9
0
9
Description
8
8
0
8
7
7
0
7
Section 22.4.3, “Transfer Delays”
6
6
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
0
5
5
6
4
4
Queued Serial Peripheral Interface (QSPI)
0
5
3
3
0
4
DTL
2
2
0
3
1
1
Access: User read/write
0
0
for information on
1
2
B
0
1
22-5
0
0