MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 573
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. A subqueue is
defined by setting the pause bit in the last CCW of the subqueue.
Figure 28-22
shown with four CCWs in each subqueue and queue 2 has two CCWs in each subqueue.
The operating mode selected for queue 1 determines what type of trigger event causes the execution of
each of the subqueues within queue 1. Similarly, the operating mode for queue 2 determines the type of
trigger event required to execute each of the subqueues within queue 2.
For example, when the external trigger rising edge continuous-scan mode is selected for queue 1, and there
are six subqueues within queue 1, a separate rising edge is required on the external trigger signal after
every pause to begin the execution of each subqueue (refer to
The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each subqueue.
Once a subqueue is initiated, each CCW is executed sequentially until the last CCW in the subqueue is
executed and the pause state is entered. Execution can only continue with the next CCW, which is the
beginning of the next subqueue. A subqueue cannot be executed a second time before the overall queue
execution has been completed.
Freescale Semiconductor
•
•
completion or the paused state, queue 2 begins executing again. The programming of the RESUME
bit in QACR2 determines which CCW is executed in queue 2.
When simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and
the queue 2 status is changed to trigger pending.
When subqueues are paused
shows the CCW format and an example of using pause to create subqueues. Queue 1 is
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure
28-22).
Queued Analog-to-Digital Converter (QADC)
28-35
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