MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 104
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Cache
4.2.2
The ACRs provide a definition of memory reference attributes for two memory regions (one per ACR).
This set of effective attributes is defined for every memory reference using the ACRs or the set of default
attributes contained in the CACR. The ACRs are examined for every processor memory reference not
mapped to the flash or SRAM memories.
The ACRs are 32-bit, write-only supervisor control register. They are accessed in the CPU address space
via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be read when in
background debug mode (BDM). Therefore, the register diagram,
system reset, both registers are disabled with ACRn[EN] cleared.
4-6
Reset – – – – – – – – – – – – – – – –
BDM: 0x004 (ACR0)
W
R
0x005 (ACR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
CACR
[DISI]
Access Control Registers (ACR0, ACR1)
1
0
0
0
0
0
IPSBAR space should not be cached. The combination of the CACR
defaults and the two ACRn registers must define the non-cacheable attribute
for this address space.
AB
[DISD]
CACR
0
0
0
0
0
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
CACR
[INVI]
Table 4-4. Cache Invalidate All as Defined by CACR
0
0
1
1
x
x
Figure 4-3. Access Control Registers (ACRn)
[INVD]
CACR
AM
0
1
0
1
x
x
Split Instruction/
Data Cache
Split Instruction/
Data Cache
Split Instruction
Data Cache
Split Instruction/
Data Cache
Instruction Cache
Data Cache
Configuration
NOTE
EN
0
14
–
SM
13
–
Invalidate 2 KByte instruction cache
Invalidate all entries in 1-KByte instruction
cache and 1-KByte data cache
Invalidate only 1 KByte data cache
Invalidate only 1 KByte instruction cache
No invalidate
Invalidate 2 KByte data cache
12
0
0
11
0
0
Figure
10
0
0
9
0
0
Operation
4-3, is shown as read/write. At
0
0
8
0
0
7
CM BWE
6
–
Access: Supervisor write-only
Freescale Semiconductor
–
5
0
0
4
BDM read/write
0
0
3
WP
–
2
0
0
1
0
0
0
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