MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 622
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug Support
30.3.1
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data
output.
Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses
associated with taken branches which use a variant addressing mode, that is, RTE and RTS instructions,
JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception
vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the processor uses the debug pins to output the following sequence of
information on successive processor clock cycles:
Another example of a variant branch instruction would be a JMP (A0) instruction.
PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was programmed to
display the lower 2 bytes of an address).
PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the
subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in
least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the
30-4
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the
3. The new target address is optionally available on subsequent cycles using the DDATA port. The
Hex
0xE
0xF
CLKOUT
PST[3:0]
DDATA
DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes).
Binary
PST
1110
1111
Begin Execution of Taken Branch (PST = 0x5)
Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP
instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display
0xE until the stopped mode is exited
Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF
until the processor is restarted or reset. (see
Figure 30-3. Example JMP Instruction Output on PST/DDATA
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
0x5
0x0
Table 30-2. Processor Status Encoding (continued)
0x9
0x0
.
default
A[3:0]
Section 30.5.1, “CPU
Definition
default
A[7:4]
A[11:8]
default
Halt”)
Figure 30-3
A[15:12]
default
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