MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 571

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) field in the
CCW, the timing changes to that shown in
Table (CCW)
potential conversion time by two QCLKs. When using the bypass mode, the external circuit should be of
low source impedance (typically less than 10 kΩ). Also, the loading effects on the external circuitry of the
QADC need to be considered, because the benefits of the sample amplifier are not present.
28.7.3.3 Channel Decode and Multiplexer
The internal multiplexer selects one of the eight analog input signals for conversion. The selected input is
connected to the sample buffer amplifier or to the sample capacitor. The multiplexer also includes positive
and negative stress protection circuitry, which prevents deselected channels from affecting the selected
channel when current is injected into the deselected channels.
28.7.3.4 Sample Buffer
The sample buffer is used to raise the effective input impedance of the A/D converter, so that external
factors (higher bandwidth or higher impedance) are less critical to accuracy. The input voltage is buffered
onto the sample capacitor to reduce crosstalk between channels.
28.7.3.5 Comparator
The comparator output feeds into the SAR, which accumulates the A/D conversion result sequentially,
beginning with the MSB.
Freescale Semiconductor
QCLK
for more information on the BYP field. The initial sample time is eliminated, reducing the
QCLK
Because of internal RC time constants, use of a two QCLK sample time in
bypass mode will cause serious errors when operating the QADC at high
frequencies.
2 Cycles
Sample
Sample Time
Buffer
Time:
n CYCLES
(2,4,8,16)
Sample
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Sample Time
Time:
Figure 28-21. Bypass Mode Conversion Timing
(2,4,8,16)
n Cycles
Sample
Time:
Final
Figure 28-20. Conversion Timing
Successive Approximation Resolution Sequence
Figure
Successive Approximation Resolution Sequence
28-21. See
NOTE
Resolution
10 Cycles
Time:
Resolution
10 Cycles
Section 28.6.7, “Conversion Command Word
Time:
Queued Analog-to-Digital Converter (QADC)
28-33