DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 140

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 8-7:
DS70291E-page 140
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
PWCOL7
XWCOL7
R/C-0
R/C-0
PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1 = Write collision detected
0 = No write collision detected
PWCOL6
XWCOL6
R/C-0
R/C-0
DMACS0: DMA CONTROLLER STATUS REGISTER 0
W = Writable bit
‘1’ = Bit is set
PWCOL5
XWCOL5
R/C-0
R/C-0
PWCOL4
XWCOL4
R/C-0
R/C-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PWCOL3
XWCOL3
R/C-0
R/C-0
C = Clear only bit
PWCOL2
XWCOL2
R/C-0
R/C-0
© 2011 Microchip Technology Inc.
x = Bit is unknown
PWCOL1
XWCOL1
R/C-0
R/C-0
PWCOL0
XWCOL0
R/C-0
R/C-0
bit 8
bit 0