DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 147

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.4
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in
The output of the primary oscillator or FRC, denoted as
‘F
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale
PLLPRE<4:0> bits (CLKDIV<4:0>).
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(F
generates device operating speeds of 6.25-40 MIPS.
FIGURE 9-2:
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
IN
Source (Crystal, External Clock
OSC
or Internal RC)
’, is divided down by a prescale factor (N1) of 2, 3,
Note 1: This frequency range must be satisfied at all times.
) is in the range of 12.5 MHz to 80 MHz, which
factor
PLL CONFIGURATION
‘N1’
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/
X04 PLL BLOCK DIAGRAM
Figure
is
9-2.
selected
Divide by
PLLPRE
2-33
N1
using
0.8-8.0 MHz
the
X
(1)
For a primary oscillator or FRC oscillator, output ‘F
the PLL output ‘F
EQUATION 9-2:
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
• If PLLDIV<8:0> = 0x1E, then
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
EQUATION 9-3:
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8 MHz - 8 MHz.
M = 32. This yields a VCO output of 5 x 32 = 160
MHz, which is within the 100 MHz - 200 MHz
ranged needed.
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
Divide by
PLLDIV
F
2-513
VCO
CY
M
=
100-200 MHz
F
-------------
OSC
F
2
F
VCO
OSC
OSC
=
’ is given by:
=
1
-- -
2
F
XT WITH PLL MODE
EXAMPLE
⎛
⎝
PLLPOST
Divide by
(1)
F
10000000 32
-----------------------------------
OSC
2, 4, 8
IN
N2
•
2 2
CALCULATION
⎛
⎝
•
------------------- -
N1 N2
M
•
12.5-80 MHz
•
DS70291E-page 147
⎞
⎠
⎞
⎠
=
40MIPS
(1)
F
OSC
IN
’,