DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 420

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
TABLE A-2:
DS70291E-page 420
Section 11.0 “I/O Ports”
Section 18.0 “Serial Peripheral
Interface (SPI)”
Section 20.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Section 21.0 “Enhanced CAN
(ECAN™) Module”
Section 22.0 “10-bit/12-bit Analog-
to-Digital Converter (ADC1)”
Section 23.0 “Audio Digital-to-
Analog Converter (DAC)”
Section 24.0 “Comparator Module”
Section 25.0 “Real-Time Clock and
Calendar (RTCC)”
Section 28.0 “Special Features”
Section Name
MAJOR SECTION UPDATES (CONTINUED)
Removed Table 11-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added paragraph on ADPCFG register default values to Section 11.3
“Configuring Analog Port Pins”.
Added Note box regarding PPS functionality with input mapping to
Section 11.6.2.1 “Input Mapping”.
Added Note 2 and 3 to the SPIxCON1 register (see Register 18-2).
Updated the Notes in the UxMode register (see Register 20-1).
Updated the UTXINV bit settings in the UxSTA register and added Note 1
(see Register 20-2).
Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see
Register 21-1).
Replaced the ADC1 Module Block Diagrams with new diagrams (see
Figure 22-1 and Figure 22-2).
Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1
Control Register 3 (AD1CON3) (see Register 22-3).
Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see
Register 22-7).
Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)
(see Register 22-8).
Updated the midpoint voltage in the last sentence of the first paragraph.
Updated the voltage swing values in the last sentence of the last paragraph
in Section 23.3 “DAC Output Format”.
Updated the Comparator Voltage Reference Block Diagram
(see Figure 24-2).
Updated the minimum positive adjust value for CAL<7:0> in the RTCC
Calibration and Configuration (RCFGCAL) Register (see Register 25-1).
Added Note 1 to the Device Configuration Register Map (see Table 28-1).
Updated Note 1 in the dsPIC33F Configuration Bits Description (see
Table 28-2).
Update Description
© 2011 Microchip Technology Inc.