DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 314

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 27-1:
DS70291E-page 314
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
PMPEN
R/W-0
R/W-0
CSF1
2:
28-pin devices do not have PMA<10:2>.
These bits have no effect when their corresponding pins are used as address lines.
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits
11 =Reserved
10 =All 16 bits of address are multiplexed on PMD<7:0> pins
01 =Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
00 =Address and data appear on separate pins
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF1:CSF0: Chip Select Function bits
11 = Reserved
10 = PMCS1 functions as chip select
0x = PMCS1 functions as address bit 14
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
Unimplemented: Read as ‘0’
CS1P: Chip Select 1 Polarity bit
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
R/W-0
CSF0
U-0
—
PMCON: PARALLEL PORT CONTROL REGISTER
PMA<10:8>
W = Writable bit
‘1’ = Bit is set
R/W-0
PSIDL
R/W-0
ALP
(1)
ADRMUX1
(2)
(2)
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
R/W-0
CS1P
(1)
PTBEEN
R/W-0
R/W-0
BEP
(1)
© 2011 Microchip Technology Inc.
x = Bit is unknown
PTWREN
WRSP
R/W-0
R/W-0
PTRDEN
R/W-0
R/W-0
RDSP
bit 8
bit 0