DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 5

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Communication Modules:
• 4-wire SPI (up to two modules):
• I
• UART (up to two modules):
• Enhanced CAN (ECAN™ module) 2.0B active:
• Parallel Master Slave Port (PMP/EPSP):
• Programmable Cyclic Redundancy Check (CRC):
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
- Framing supports I/O interface to simple
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN 2.0 bus support
- IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
- Supports 8-bit or 16-bit data
- Supports 16 address lines
- Programmable bit length for the CRC
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
2
C™:
codecs
sampling modes
monitoring
Transmission Requests
generator polynomial (up to 16-bit length)
input
®
encoding and decoding in hardware
Packaging:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
Note:
See
features per device.
Table 1
for the exact peripheral
DS70291E-page 5