DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 325

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.2
All
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices power their core digital logic at a nominal
2.5V. This can create a conflict for designs that are
required to operate at a higher typical voltage, such as
3.3V. To simplify system design, all devices in the
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 family incorporate an
on-chip regulator that allows the device to run its core
logic from V
The regulator provides power to the core from the other
V
(less than 5 Ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure
regulator. The recommended value for the filter capac-
itor is provided in
“Electrical
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 28-1:
© 2011 Microchip Technology Inc.
DD
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note:
Note 1: These are typical operating voltages. Refer
pins. When the regulator is enabled, a low-ESR
Tantalum
28-1). This helps to maintain the stability of the
10 µF
On-Chip Voltage Regulator
of
C
,
2: It is important for the low-ESR capacitor to
EFC
STARTUP
it takes approximately 20 μs for the on-chip
Characteristics”.
It is important for the low-ESR capacitor to
be placed as close as possible to the V
pin.
DD
to
“DC Characteristics”
ranges of V
be placed as close as possible to the V
pin.
.
3.3V
Table 31-13
Table 31-13
the
is applied every time the device
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
DD
DD
CAP
SS
dsPIC33F
STARTUP
and V
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04
located in
located in
CAP
for the full operating
, code execution is
.
(1)
Section 31.1
Section 31.0
CAP
CAP
CAP
pin
28.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage V
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit, if enabled, contin-
ues to operate while in Sleep or Idle modes and resets
the device should VDD fall below the BOR threshold
voltage.
Brown-Out Reset (BOR)
CAP
. The main purpose of the
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