DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 419

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision C (May 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
• Changed all instances of V
The other changes are referenced by their respective
section in the following table.
TABLE A-2:
© 2011 Microchip Technology Inc.
“High-Performance, 16-bit Digital
Signal Controllers”
Section 1.0 “Device Overview”
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Section 3.0 “CPU”
Section 4.0 “Memory Organization”
Section 5.0 “Flash Program
Memory”
Section 9.0 “Oscillator
Configuration”
Section 10.0 “Power-Saving
Features”
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
OSCO to OSC2
V
CAP
to V
CAP
Section Name
/V
DDCORE
MAJOR SECTION UPDATES
DDCORE
and V
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to V
Updated AV
Added new section to the data sheet that provides guidelines on getting
started with 16-bit Digital Signal Controllers.
Updated CPU Core Block Diagram with a connection from the DSP Engine
to the Y Data Bus (see Figure 3-1).
Vertically extended the X and Y Data Bus lines in the DSP Engine Block
Diagram (see Figure 3-3).
Updated Reset value for CORCON in the CPU Core Register Map (see
Table 4-1).
Removed the FLTA1IE bit (IEC3) from the Interrupt Controller Register Map
(see Table 4-4).
Updated bit locations for RPINR25 in the Peripheral Pin Select Input
Register Map (see Table 4-24).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-36).
Updated Section 5.3 “Programming Operations” with programming time
formula.
Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock Sources”.
Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
Added the following registers:
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
DDCORE
/
DD
in the PINOUT I/O Descriptions (see Table 1-1).
Update Description
SS
.
DS70291E-page 419