DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 25

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.0
3.1
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and
interruptible at any time.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices have
sixteen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th
working register (W15) operates as a software Stack
Pointer (SP) for interrupts and calls.
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note 1: This data sheet summarizes the features
REPEAT
2: Some registers and associated bits
CPU
Overview
flow,
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 2. CPU”
(DS70204) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
instructions,
the
double-word
dsPIC33FJ32MC302/304,
both
move
of
family
which
(MOV.D)
and
are
of
in
There
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 is capable of exe-
cuting a data (or program data) memory read, a work-
ing register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in
the programmer’s model for the dsPIC33FJ32MC302/
304,
dsPIC33FJ128MCX02/X04 is shown in
3.2
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
are
Data Addressing Overview
two
dsPIC33FJ64MCX02/X04
classes
dsPIC33FJ64MCX02/X04
of
instruction
DS70291E-page 25
Figure
Figure
3-1, and
3-2.
in
and
the