DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 169

16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB

DSPIC33FJ128MC804-H/ML

Manufacturer Part Number
DSPIC33FJ128MC804-H/ML
Description
16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheet

Specifications of DSPIC33FJ128MC804-H/ML

Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b, D/A 6x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 140°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
11.7
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 family of devices
implement 33 registers for remappable peripheral
configuration:
• 20 Input Remappable Peripheral Registers:
• 13 Output Remappable Peripheral Registers:
REGISTER 11-1:
© 2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-8
bit 7-0
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
- RPINR0-RPINR1, RPINR3-RPINR4,
- RPOR0-RPOR12
Note:
RPINR7, RPINR10-RPINR21, PRINR23, and
PRINR26
U-0
U-0
Peripheral Pin Select Registers
Input and Output Register values can only
be
(OSCCON<6>)
Section 11.6.3.1
Lock”
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111 = Input tied to V
11001 = Input tied to RP25
00001 = Input tied to RP1
00000 = Input tied to RP0
Unimplemented: Read as ‘0’
changed
for a specific command sequence.
U-0
U-0
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
if
is
W = Writable bit
‘1’ = Bit is set
“Control
the
set
U-0
U-0
IOLOCK
to
SS
‘0’.
Register
R/W-1
See
U-0
bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-1
U-0
INT1R<4:0>
R/W-1
U-0
x = Bit is unknown
R/W-1
U-0
DS70291E-page 169
R/W-1
U-0
bit 8
bit 0

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