DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 154

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
REGISTER 9-5:
DS70291E-page 154
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-14
bit 13
bit 12-11
bit 10-8
bit 7
bit 6-0
Note 1:
ASRCSEL
R/W-0
U-0
—
This register is reset only on a Power-on Reset (POR).
Unimplemented: Read as ‘0’
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider
1 = Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider
0 = PLL output (F
AOSCMD<1:0>: Auxiliary Oscillator Mode
11 = EC External Clock Mode Select
10 = XT Oscillator Mode Select
01 = HS Oscillator Mode Select
00 = Auxiliary Oscillator Disabled (default)
APSTSCLR<2:0>: Auxiliary Clock Output Divider
111 = divided by 1
110 = divided by 2
101 = divided by 4
100 = divided by 8
011 = divided by 16
010 = divided by 32
001 = divided by 64
000 = divided by 256 (default)
ASRCSEL: Select Reference Clock Source for Auxiliary Clock
1 = Primary Oscillator is the Clock Source
0 = Auxiliary Oscillator is the Clock Source
Unimplemented: Read as ‘0’
U-0
U-0
—
—
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
SELACLK
VCO
R/W-0
U-0
—
) provides the source clock for the Auxiliary Clock Divider
R/W-0
U-0
—
AOSCMD<1:0>
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-0
U-0
—
APSTSCLR<2:0>
© 2011 Microchip Technology Inc.
x = Bit is unknown
R/W-0
U-0
—
(1)
R/W-0
U-0
—
bit 8
bit 0