DSPIC33FJ128MC804-H/ML Microchip Technology, DSPIC33FJ128MC804-H/ML Datasheet - Page 203

• Manufacturer Part Number: DSPIC33FJ128MC804-H/ML
• Description: 16-bit DSC, 128KB Flash, Motor, CAN, DMA, 40 MIPS, NanoWatt 44 QFN 8x8x0.9mm TUB
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC804-H/ML

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b, D/A 6x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 140°C
• Package / Case: 44-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.0
The Input Capture module is useful in applications that
requires frequency (period) and pulse measurement.
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 devices support
up to four input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
FIGURE 14-1:
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
ICx pin
INPUT CAPTURE
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 12. Input Capture”
(DS70198) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
the
INPUT CAPTURE BLOCK DIAGRAM
dsPIC33FJ32MC302/304,
Falling Edge Mode
(16th Rising Edge)
Rising Edge Mode
(4th Rising Edge)
Prescaler Mode
Prescaler Mode
Edge Detection
Wake-up Mode
Sleep/Idle
Mode
family
and
101
100
011
010
001
ICM<2:0>
of
in
CaptureEvent
• Simple Capture Event modes:
• Capture timer value on every edge (rising and
• Prescaler Capture Event modes:
Each input capture channel can select one of two 16-
bit timers (Timer2 or Timer3) for the time base. The
selected timer can use either an internal or external
clock.
Other operational features include:
• Device wake-up from capture pin during CPU
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Use of input capture to provide additional sources
ICTMR
falling)
Sleep and Idle modes
- Interrupt optionally generated after 1, 2, 3 or
of external interrupts
Note:
- Capture timer value on every falling edge of
- Capture timer value on every rising edge of
- Capture timer value on every 4th rising
- Capture timer value on every 16th rising
4 buffer locations are filled
input at ICx pin
input at ICx pin
edge of input at ICx pin
edge of input at ICx pin
FIFO CONTROL
TMR2 TMR3
ICxBUF
ICI<1:0>
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00)
/N
FIFO
ICM<2:0>
001
111
To CPU
(In IFSx Register)
Set Flag ICxIF
DS70291E-page 203