ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 19

• Manufacturer Part Number: ATAM862P-TNSY4D
• Description: IC MCU FLASH 4K TX 433MHZ 24SSOP
• Manufacturer: Atmel

Specifications of ATAM862P-TNSY4D

• Applications: UHF ASK/FSK
• Core Processor: MARC4
• Program Memory Type: FLASH (4 kB)
• Controller Series: MARC4 4-Bit
• Ram Size: 256 x 4
• Interface: SSI
• Number Of I /o: 11
• Voltage - Supply: 1.8 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Processor Series: ATAM862x
• Core: MARC4
• Data Bus Width: 4 bit
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3.10
16.4
16.5
16.6
4551G–4BMCU–07/07
ALU
I/O Bus
Instruction Set
Interrupt Enable (I)
The interrupt enable flag globally enables or disables the triggering of all interrupt routines with
the exception of the non-maskable reset. After a reset or while executing the DI instruction, the
interrupt enable flag is reset, thus disabling all interrupts. The core will not accept any further
interrupt requests until the interrupt enable flag has been set again by either executing an EI or
SLEEP instruction.
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top two ele-
ments of the expression stack (TOS and TOS-1) and returns the result to the TOS. The ALU
operations affects the carry/borrow and branch flag in the condition code register (CCR).
Figure 16-4. ALU Zero-address Operations
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication
between the core and the on-chip peripherals take place via the I/O bus and the associated I/O
control. With the microcontroller IN and OUT instructions, the I/O bus allows a direct read or
write access to one of the 16 primary I/O addresses. More about the I/O access to the on-chip
peripherals is described in the section“”Peripheral Modules”. The I/O bus is internal and is not
accessible by the customer on the final microcontroller device, but it is used as the interface for
the microcontroller emulation (see section
The microcontroller instruction set is optimized for the high level programming language
qFORTH. Many microcontroller instructions are qFORTH words. This enables the compiler to
generate a fast and compact program code. The CPU has an instruction pipeline allowing the
controller to prefetch an instruction from EEPROM at the same time as the present instruction is
being executed. The microcontroller is a zero-address machine, the instructions contain only the
operation to be performed and no source or destination address fields. The operations are
implicitly performed on the data placed on the stack. There are one- and two-byte instructions
which are executed within 1 to 4 machine cycles. A microcontroller machine cycle is made up of
two system clock cycles (SYSCL). Most of the instructions are only one byte long and are exe-
cuted in a single machine cycle. For more information refer to the “MARC4 Programmer’s
Guide”.
SP
RAM
TOS-1
TOS-2
TOS-3
TOS-4
“Emulation” on page
CCR
ALU
104).
TOS
ATAM862-4
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